`timescale 1ns/1ns
interface PW_if(input bit sys_clk); 
 
parameter aw = 5;
parameter dw = 32;

bit                rst_n;

bit        [aw-1:0]PS_PC;
bit        [aw-1:0]PW_PC;
bit        [dw-1:0]Fet_Pkt_i;
bit        [dw-1:0]Fet_Pkt_o; 
bit                Fet_Pkt_rdy;
   
bit                DP_stall;
bit                I_FP_invalid;
bit                D_RAM_invalid;

bit                PS_io_invalid; 
bit                PW_io_invalid; 
     
bit                Int_Sev; 
bit                FP_en;
bit                DSP_core_en; 
   
//********************************************************************************************************************* 
           

clocking cb @(negedge sys_clk);
output                   rst_n,
                         PS_PC,
                         Fet_Pkt_i,
                         Fet_Pkt_rdy,
                         DP_stall,
                         I_FP_invalid,
                         D_RAM_invalid,
                         PS_io_invalid,
                         Int_Sev,
                         FP_en,
                         DSP_core_en;
                          
input                    PW_PC,
                         Fet_Pkt_o,
                         PW_io_invalid;
endclocking 


//*********************************************************************************************************************   
  

  modport TEST (clocking cb );

  modport DUT (input     rst_n,
                         PS_PC,
                         Fet_Pkt_i,
                         Fet_Pkt_rdy,
                         DP_stall,
                         I_FP_invalid,
                         D_RAM_invalid,
                         PS_io_invalid,
                         Int_Sev,
                         FP_en,
                         DSP_core_en,
                         
               output    PW_PC,
                         Fet_Pkt_o,
                         PW_io_invalid);

  modport MONITOR (input rst_n,
                         PS_PC,
                         Fet_Pkt_i,
                         Fet_Pkt_rdy,
                         DP_stall,
                         I_FP_invalid,
                         D_RAM_invalid,
                         PS_io_invalid,
                         Int_Sev,
                         FP_en,
                         DSP_core_en,
                         PW_PC,
                         Fet_Pkt_o,
                         PW_io_invalid);

endinterface
